The present invention relates, in general, to electronics and, more particularly, to methods for forming electronic devices such as semiconductor dies.
In the past, the semiconductor industry utilized various methods and equipment to etch substrates, such as semiconductor wafers. One such technique is called dry etching or plasma etching, which has been used to etch the semiconductor wafer itself, or other materials formed on the semiconductor wafer, such as insulating materials and conductive materials. One challenge with drying etching processes is accurately determining when to terminate the etching process, which is often termed “end-point” detection. Past techniques have included running one or more test wafers to determine the time and etch conditions necessary to achieve the desired results. Product wafers are then run using the results of the test wafer characterization. One problem with this approach is that it takes time to run the test wafers, which impacts manufacturing cycle-time. Also, this approach does not catch drifting processes in real time, which leads to wafers having to be re-processed to achieve the desired results or scrapped.
Other past approaches to end-point detection have included adding additional etching time to over-etch the semiconductor wafer and characterization of residual etch gases in the etch chamber. Problems with these approaches have included, for example, inaccurate measurement of real-time semiconductor material etch rates, yield losses due to under-etching and the need for reworking wafers, yield losses due to inconsistencies in etching reworked wafers including loss of passivation layer thicknesses, and required process characterization studies to determine etch recipes when new device types are implemented, which impacts cycle time and manufacturing costs.
Additional complicating factors in the manufacturability of dry etching processes have included etch rate variability caused by device types being processed, the amount of exposed semiconductor material to be removed, conductive and passivation materials used with the semiconductor wafers, and types of processes the semiconductor wafers were previously exposed to. Further, recent developments in new designs in semiconductor device topography, such as deep and wide recessed regions, have presented processing challenges because these new devices typically do not use etch stop layers. This factor makes the manufacturability of such devices difficult.
Accordingly, it is desirable to have a method that more accurately determines the amount of material removed during a dry etching processes including, for example, recess formation processes. It would be beneficial for the method to be cost effective, to be in-situ process compatible, to be manufacturable in the absence of etch stop layers, and to minimize any damage to or contamination of the processed material.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures donate the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-type regions and certain P-type regions, a person of ordinary skill in the art understands that the conductivity types can be reversed and are also possible in accordance with the present description, taking into account any necessary polarity reversal of voltages, inversion of transistor type and/or current direction, etc. For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles. Furthermore, the term major surface when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including, when used in this specification, specify: the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure. It will be appreciated by those skilled in the art that words, during, while, and when as used herein related to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action, but that there may be some small but reasonable delay, such as propagation delay, between the reaction that is initiated by the initial action. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but in some cases it may. The use of word about, approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. Unless specified otherwise, as used herein the word over or on includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact. Unless specified otherwise, as used herein the word over lapping includes orientations, placements, or relations where the specified elements can at least partly or wholly coincide or align in the same or different planes. It is further understood that the embodiments illustrated and described hereinafter suitably may have embodiments and/or may be practiced in the absence of any element that is not specifically disclosed herein.